1. Field of the Invention
The present invention relates to an only-one-polysilicon layer non-volatile memory cell, especially for the methods to improve sensing margin and reliability.
2. Description of Related Art
A non-volatile memory is a memory capable of holding stored data when the memory is not supplied with power. There are currently two types of non-volatile memories, i.e. read only memory (ROM) and flash memory.
FIG. 1 illustrates a conventional stacked polysilicon layers non-volatile memory unit cell and sensing of data thereof which was disclosed in U.S. Pat. No. 5,973,957. Referring to FIG. 1, floating polysilicon gates of transistors 101 and 102 which used to store data receive the same voltage VG and generate currents I1 and I2, respectively. A comparator CMP compares voltages generated by the currents I1 and I2 flowing through transistors 103 and 104 to detect data stored in the non-volatile memory unit cell (transistors 101 and 102), wherein each of the transistors 103 and 104 forms a diode by appropriately coupling terminals thereof and is connected to an operating voltage VCC. The major idea for this sensing scheme is to use a memory unit cell as a source of reference current. The sensing margin is greatly improved by adopting a dummy reference memory unit cell receiving similar bias variations, temperature sensitivity, and cell dimension matching with the memory cell.
FIG. 2A illustrates another prior art for a non-volatile memory unit cell and sensing of data thereof which was disclosed in U.S. Pat. No. 6,950,342. Referring to FIG. 2A, the non-volatile memory unit cell 210 includes coupling capacitors constructed by transistors M1c, M1t, M0t and M0c, and transistors M1 and M0 connected to a voltage V. The transistors M1c and M1t couple received voltages V1c and V1t to the floating polysilicon gate Fg1, respectively. The transistors M0c and M0t couple received voltages V0c and V0t to the floating polysilicon gate Fg0, respectively. A current sensor 220 senses the data stored in the non-volatile memory unit cell 210 by measuring the currents I1 and I0 flowing out of the transistors M1 and M0. A sensing margin is also improved by comparing a memory unit cell and a dummy reference memory cell.
It is noted that electric leakage may occur due to defect of the gate oxide of the transistor M1 or M0 after the non-volatile memory unit cell 210 stores data for cycling induced oxide stress or a long storage time. If this electric leakage occurs, the charges originally stored at the transistor M1 or M0 would decrease and on-state current would also decrease over storage time as shown in FIG. 2B. As such, the memory window A1 between a current curve CV1 when the transistor M1 or M0 turns on and a current curve CV2 when the transistors M1 or M0 turns off would decrease to the memory window A2 with increasing of the storage time. Accordingly, the sensing result of the current sensor 220 may be incorrect which would result in misjudgement of the data stored in the non-volatile memory unit cell 210.
To read a memory cell's data correctly, a memory window is a critical design parameters for a non-volatile memory chip. There are some factors which will affect the memory window such as a mismatching between a memory unit cell and a reference device (device dimension, temperature, operation bias, for examples), a critical leakage path surrounding the floating polysilicon gate of the memory unit cell (floating polysilicon gate oxide, sidewall spacer, for examples). In this background, several improved techniques are disclosed and targeting to solve these issues, improving the memory window of non-volatile memory chip.